Torre Arnanz, Eduardo De La eduardo.delatorre@upm.es
Actividades
- Artículos 36
- Libros 1
- Capítulos de libro 5
- Congresos 103
- Documentos de trabajo 0
- Informes técnicos 0
- Proyectos de investigación 35
- Tesis dirigidas 11
- Patentes o licencias de software 0
Welcome to the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP) in Madrid, Spain
- De La Torre E
- Pillement S
Conference On Design And Architectures For Signal And Image Processing, Dasip - 1/1/2015
10.1109/dasip.2014.7115597 Ver en origen
- ISSN 21649766
Using SRAM based FPGAs for power-aware high performance wireless sensor networks
- Valverde, Juan
- Otero, Andres
- Lopez, Miguel
- Portilla, Jorge
- de la Torre, Eduardo
- Riesgo, Teresa
Sensors (p. 2667-2692) - 1/3/2012
10.3390/s120302667 Ver en origen
- ISSN 14248220
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis
- He, Wei
- Bhasin, Shivam
- Otero, Andres
- Graba, Tarik
- de la Torre, Eduardo
- Danger, Jean-Luc;
Iet Information Security (p. 1-13) - 1/1/2015
10.1049/iet-ifs.2013.0058 Ver en origen
- ISSN 17518709
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing
- Salvador, Ruben
- Otero, Andres
- Mora, Javier
- de la Torre, Eduardo
- Riesgo, Teresa
- Sekanina, Lukas;
Ieee Transactions On Computers (p. 1481-1493) - 22/7/2013
10.1109/tc.2013.78 Ver en origen
- ISSN 00189340
Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression
- Rodriguez, Alfonso
- Santos, Lucana
- Sarmiento, Roberto
- De La Torre, Eduardo;
Ieee Access (p. 10644-10652) - 1/1/2019
10.1109/access.2019.2892308 Ver en origen
- ISSN 21693536
Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation
- Pérez A
- Rodríguez A
- Otero A
- Arjona DG
- Jiménez-Peralo Á
- Verdugo MÁ
- De La Torre E
Ieee Access (p. 59891-59905) - 1/1/2020
10.1109/access.2020.2983308 Ver en origen
- ISSN 21693536
Reconfigurable Networks on Chip: DRNoC architecture
- Krasteva, Yana E.
- de la Torre, Eduardo
- Riesgo, Teresa;
Journal Of Systems Architecture (p. 293-302) - 1/7/2010
10.1016/j.sysarc.2010.04.003 Ver en origen
- ISSN 13837621
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
- Mora, Javier
- Salvador, Ruben
- de la Torre, Eduardo;
Genetic Programming And Evolvable Machines (p. 155-186) - 1/6/2019
10.1007/s10710-018-9340-5 Ver en origen
- ISSN 13892576
Multi-grain reconfigurable and scalable overlays for hardware accelerator composition
- Zamacola R
- Otero A
- de la Torre E
Journal Of Systems Architecture - 1/1/2021
10.1016/j.sysarc.2021.102302 Ver en origen
- ISSN 13837621
Lossy hyperspectral image compression on a reconfigurable and fault-tolerant fpga-based adaptive computing platform†
- Barrios Y
- Rodríguez A
- Sánchez A
- Pérez A
- López S
- Otero A
- de la Torre E
- Sarmiento R
Electronics (p. 1-23) - 1/10/2020
10.3390/electronics9101576 Ver en origen
- ISSN 08834989
Wireless Sensor Networks: From Real World to System Integration - Alternative Hardware Approaches
Comprehensive Materials Processing (p. 353-373) - 1/1/2014
Run-time scalable architecture for deblocking filtering in H.264/AVC and SVC video codecs
- Teresa Cervero
- S. López
- G. Gallicó
- OTERO MARNOTES, JOSE ANDRES
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
Embedded Systems Design With Fpgas (p. 173-199) - 1/11/2013
FPGAs and reconfigurable systems
- Rodriguez-Andina JJ
- de la Torre E
Fundamentals Of Industrial Electronics (p. 24-1-24-18) - 19/4/2016
- iMarina
Dynamic reconfigurable NoC (DRNoC) architecture: Application to fast NoC emulation
- Krasteva Y
- de la Torre E
- Riesgo T
Dynamic Reconfigurable Network-On-Chip Design: Innovations For Computational Processing And Communication (p. 220-254) - 1/12/2010
Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation
- Krasteva Y
- De La Torre E
- Riesgo T
Ieee Annual Conference Of The Ieee Industrial Electronics Society (Iecon'08) (p. 0-0) - 10/11/2008
10.1109/iecon.2008.4758347 Ver en origen
- iMarina
- iMarina
Virtex II FPGA bitstream manipulation: Application to reconfiguration control systems
- Krasteva Y
- De La Torre E
- Riesgo T
- Joly D
Proceedings - 2006 International Conference On Field Programmable Logic And Applications, Fpl (p. 717-720) - 1/12/2006
Using Partial Reconfiguration for SoC Design and Implementation
- F. Tobajas
- TORRE ARNANZ, EDUARDO DE LA
- PORTILLA BERRUECO, JORGE
Proceedings Of Spie - The International Society For Optical Engineering (p. 736.306-1.736.304) - 14/9/2009
10.1117/12.821718 Ver en origen
- ISSN 0277786X
- iMarina
- iMarina
Use of standards in electronic design
- Riesgo T
- de la Torre E
- Torroja Y
- Uceda J
Iecon-2002: Proceedings Of The 2002 28th Annual Conference Of The Ieee Industrial Electronics Society, Vols 1-4 (p. 407-412) - 1/12/1996
- iMarina
Towards fine and medium grain dynamic functional extraction for HW/SW acceleration
- Matev, V.
- de la Torre, E.
- Riesgo, T.;
2007 3rd Southern Conference On Programmable Logic, Proceedings (p. 93-+) - 27/9/2007
Towards fine and medium grain dynamic functional extraction
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
- STEFANOV MATEV, VLADIMIR
1/2/2007
- iMarina
Teaching hybrid HW/SW embedded system design using FPGA-based devices
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
- Rodriguez Medina, Alfonso
- PORTILLA BERRUECO, JORGE
2016 Conference On Design Of Circuits And Integrated Systems, Dcis 2016 - Proceedings (p. 161-166) - 6/2/2017
10.1109/dcis.2016.7845372 Ver en origen
- iMarina
- iMarina
Teaching embedded systems and microcontrollers using scale models
- Torroja, Y
- Garcia, O
- Riesgo, T
- de la Torre, E
Iecon-2002: Proceedings Of The 2002 28th Annual Conference Of The Ieee Industrial Electronics Society, Vols 1-4 (p. 2180-2183) - 1/12/2005
TESTING VLSI CIRCUITS FROM VHDL DESCRIPTIONS
- RIESGO, T
- TORROJA, Y
- DELATORRE, E
- UCEDA, J;
Proceedings Of The 1992 International Conference On Industrial Electronics, Control, Instrumentation, And Automation, Vols 1-3 (p. 1052-1057) - 1/1/1992
Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs
- Krasteva Y
- Jimeno A
- De La Torre E
- Riesgo T
Proceedings Of The International Workshop On Rapid System Prototyping (p. 77-83) - 18/10/2005
10.1109/rsp.2005.45 Ver en origen
- ISSN 10746005
- iMarina
- iMarina
Este/a investigador/a no tiene documentos de trabajo.
Este/a investigador/a no tiene informes técnicos.
CARRYING OUT OF THALES ALENIA SPACE ESPAÑA YEAR ROUND CONTRACT FOR 2016-2017
- ALOU CERVERA, PEDRO (Colaborador/a)
- RIESGO ALCAIDE, TERESA (Colaborador/a)
- TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))
Ejecución: 01-09-2016 - 10-03-2022
Tipo: Interno
- iMarina
Artificial Intelligence using Quantum measured Information for realtime distributed systems at the edge
- GALLEGO ROMAN, JUAN (Miembro del equipo de trabajo)
- KATEBZADEH, MARYAM (Miembro del equipo de trabajo)
- Rodriguez Medina, Alfonso (Participante)
- TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))
- PORTILLA BERRUECO, JORGE (Participante)
- OTERO MARNOTES, JOSE ANDRES (Participante)
Ejecución: 01-12-2022 - 30-11-2025
Tipo: Nacional
Importe financiado: 249134,38 Euros.
- iMarina
An Advanced Circular and Agile Manufacturing Ecosystem based on rapid reconfigurable manufacturing process and individualized consumer preferences
- Rodriguez Medina, Alfonso (Participante)
- TORRE ARNANZ, EDUARDO DE LA (Participante)
- ZAMACOLA ALCALDE, RAFAEL MARIA (Participante)
- HERNANDEZ LORITE, ROGELIO (Participante)
- ENCINAS ANCHUSTEGUI, JUAN (Participante)
- PORTILLA BERRUECO, JORGE (Investigador principal (IP))
- UCEDA ANTOLIN, JAVIER (Participante)
- MUJICA ROJAS, GABRIEL NOE (Participante)
- OTERO MARNOTES, JOSE ANDRES (Participante)
Ejecución: 01-01-2020 - 31-12-2023
Tipo: Internacional
Importe financiado: 522625,00 Euros.
- iMarina
Actividad 4.7 del proyecto Investigación experimental en tecnologías innovadoras para una comunidad energética eficiente y sostenible
- TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))
Ejecución: 01-09-2021 - 31-12-2023
Tipo: Nacional
- iMarina
ALMACENAMIENTO INTELIGENTE BASADO EN BATERÍAS DE SEGUNDA VIDA PARA INTEGRACIÓN DE RENOVABLES
- RIQUELME DOMINGUEZ, JOSE MIGUEL (Participante)
- Castillo Sierra NA, Rafael (Miembro del equipo de trabajo)
- Castillo Sierra NA, Rafael (Investigador/a)
- RODRIGUEZ ARRIBAS, JAIME (Participante)
- OTERO MARNOTES, JOSE ANDRES (Participante)
- CASTRO FERNANDEZ, ROSA MARIA DE (Participante)
- MARIÑO ANDRES, RODRIGO (Participante)
- FRANCES ROGER, AIRAN (Participante)
- TORRE ARNANZ, EDUARDO DE LA (Participante)
- RAMIREZ PRIETO, DIONISIO (Investigador principal (IP))
Ejecución: 01-12-2022 - 30-11-2024
Tipo: Nacional
Importe financiado: 166750,00 Euros.
- iMarina
Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: He, Wei
1/1/2014
- iMarina
Runtime Adaptive Hardware/Software Execution in Complex Heterogeneous Systems
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Suriano, Leonardo
31/1/2021
- iMarina
Run-Time Scalable Hardware for Reconfigurable Systems
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Otero Marnotes, Andres
1/1/2014
- iMarina
Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems
- PORTILLA BERRUECO, JORGE (Director)
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Valverde Alcalá, Juan
1/1/2015
- iMarina
Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Esteves Krasteva, Yana
1/1/2009
- iMarina
Real-time and dependability assessment of hw-accelerated space applications for reconfigurable MPSoCs
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Pérez García, Arturo
12/5/2023
- iMarina
Parametric and structural self-adaptation of embedded systems using evolvable hardware
- SEKANINA, Lukáš (Director)
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Salvador Perea, Rubén
1/1/2015
- iMarina
Emulación en prototipos basados en fpgas: métodos de depuración mediante inserción de lógica compatible con el estándar ieee-1149.1
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: GARCIA VALDERAS, Mario
1/1/2004
- iMarina
Design Methodologies and Architectures for Just-in-Time Hardware Composition of Multi Grain Reconfigurable Accelerators
- Otero Marnotes, Andrés (Director)
- TORRE ARNANZ, EDUARDO DE LA (Director)
- OTERO MARNOTES, JOSE ANDRES (Codirector) Doctorando: Zamacola Alcalde, Rafael María
4/7/2022
- iMarina
Este/a investigador/a no tiene patentes o licencias de software.
Grupos de investigación
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Grupo en Tecnología Electrónica Aplicada (GTEA)
Rol: Investigador Principal
Perfiles de investigador/a
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ORCID
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Publons
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Scopus Author ID