Torre Arnanz, Eduardo De La eduardo.delatorre@upm.es
Actividades
- Artículos 36
- Libros 1
- Capítulos de libro 5
- Congresos 103
- Documentos de trabajo 0
- Informes técnicos 0
- Proyectos de investigación 35
- Tesis dirigidas 11
- Patentes o licencias de software 0
Foreword
- Riesgo T
- Uceda J
- Portilla J
- De La Torre E
1/1/2014
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo(3) Framework
- Rodriguez, Alfonso
- Valverde, Juan
- Portilla, Jorge
- Otero, Andres
- Riesgo, Teresa
- de la Torre, Eduardo;
Sensors - 8/6/2018
10.3390/s18061877 Ver en origen
- ISSN 14248220
Using SRAM based FPGAs for power-aware high performance wireless sensor networks
- Valverde, Juan
- Otero, Andres
- Lopez, Miguel
- Portilla, Jorge
- de la Torre, Eduardo
- Riesgo, Teresa
Sensors (p. 2667-2692) - 1/3/2012
10.3390/s120302667 Ver en origen
- ISSN 14248220
A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images
- Ortiz, Alberto
- Rodriguez, Alfonso
- Guerra, Raul
- Lopez, Sebastian
- Otero, Andres
- Sarmiento, Roberto
- de la Torre, Eduardo;
Remote Sensing - 1/11/2018
10.3390/rs10111790 Ver en origen
- ISSN 20724292
Letter from the guest editors of the special issue on DCIS 2014
- de la Torre E
- Portilla J
- Riesgo T
Microprocessors And Microsystems (p. 919-919) - 1/11/2015
10.1016/j.micpro.2015.11.006 Ver en origen
- ISSN 01419331
Accelerating the evolution of a systolic array-based evolvable hardware system
- Mora, Javier
- de la Torre, Eduardo;
Microprocessors And Microsystems (p. 144-156) - 1/2/2018
10.1016/j.micpro.2017.12.001 Ver en origen
- ISSN 01419331
Introduction to Special issue on Reconfigurable computing and FPGAs
- Cumplido, Rene
- de la Torre, Eduardo
- Feregrino-Uribe, Claudia
- Wirthlin, Michael;
Microprocessors And Microsystems (p. 541-542) - 29/10/2015
10.1016/j.micpro.2015.08.006 Ver en origen
- ISSN 01419331
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping
Microprocessors And Microsystems - 1/11/2019
10.1016/j.micpro.2019.102882 Ver en origen
- ISSN 01419331
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic
- He, Wei
- Otero, Andres
- de la Torre, Eduardo
- Riesgo, Teresa;
Microprocessors And Microsystems (p. 899-910) - 1/1/2014
10.1016/j.micpro.2014.02.005 Ver en origen
- ISSN 01419331
Introduction to Special issue on FPGA Devices and Applications
- Athanas, Peter
- Cumplido, Rene
- Feregrino-Uribe, Claudia
- de la Torre, Eduardo;
Microprocessors And Microsystems (p. 843-844) - 1/1/2014
10.1016/j.micpro.2014.11.001 Ver en origen
- ISSN 01419331
Adaptivity and Self-awareness of CPSs and CPSoSs
- De La Torre E
Heterogeneous Cyber Physical Systems Of Systems (p. 37-60) - 1/1/2021
- iMarina
FPGAs and reconfigurable systems
- Rodriguez-Andina JJ
- de la Torre E
Fundamentals Of Industrial Electronics (p. 24-1-24-18) - 19/4/2016
- iMarina
Run-time scalable architecture for deblocking filtering in H.264/AVC and SVC video codecs
- Teresa Cervero
- S. López
- G. Gallicó
- OTERO MARNOTES, JOSE ANDRES
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
Embedded Systems Design With Fpgas (p. 173-199) - 1/11/2013
Dynamic reconfigurable NoC (DRNoC) architecture: Application to fast NoC emulation
- Krasteva Y
- de la Torre E
- Riesgo T
Dynamic Reconfigurable Network-On-Chip Design: Innovations For Computational Processing And Communication (p. 220-254) - 1/12/2010
Wireless Sensor Networks: From Real World to System Integration - Alternative Hardware Approaches
Comprehensive Materials Processing (p. 353-373) - 1/1/2014
Space Design Exploration of a Viterbi-based ECC Encoding/Decoding Scheme by Wireless Transmission Emulation
- A. González
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
- PEÑA RAMOS, EDUARDO
1/11/2007
- iMarina
CAD in test
- Riesgo T
- de la Torre E
- Torroja Y
- Olias E
- Uceda J
(p. 33-38) - 1/12/1995
- iMarina
Towards fine and medium grain dynamic functional extraction
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
- STEFANOV MATEV, VLADIMIR
1/2/2007
- iMarina
Creating partially reconfigurable systems
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
5/11/2007
- iMarina
A set of hardware components for a reconfigurable control and communications board
- Casado F
- Machado F
- Riesgo T
- De La Torre E
- Torroja Y
- Uceda J
(p. 1707-1712) - 1/1/2000
Power management techniques in an FPGA-based WSN node for high performance applications
- Miguel Lombardo
- Julio Camarero
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
- PORTILLA BERRUECO, JORGE
Recosoc 2012 - 7th International Workshop On Reconfigurable And Communication-Centric Systems-On-Chip, Proceedings (p. 1-5) - 23/11/2012
10.1109/recosoc.2012.6322888 Ver en origen
- iMarina
- iMarina
Analysis of design alternatives on using dynamic and partial reconfiguration in a space application
- RIESGO ALCAIDE, TERESA
- TORRE ARNANZ, EDUARDO DE LA
Proceedings Of The Second European Workshop On Exo-Astrobiology (p. 1-4) - 1/9/2014
- ISSN 03796566
- iMarina
Highly configurable control boards: A tool and a design experience
- de la Torre, E
- Riesgo, T
- Uceda, J
- Macip, E
- Rizzi, M;
Proceedings Of The International Workshop On Rapid System Prototyping (p. 174-179) - 1/1/2000
10.1109/iwrsp.2000.855218 Ver en origen
- ISSN 10746005
Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs
- Krasteva Y
- Jimeno A
- De La Torre E
- Riesgo T
Proceedings Of The International Workshop On Rapid System Prototyping (p. 77-83) - 18/10/2005
10.1109/rsp.2005.45 Ver en origen
- ISSN 10746005
- iMarina
- iMarina
Distributed implementation of an ATPG system using dynamic fault allocation
- AGUADO, MJ
- DELATORRE, E
- MIRANDA, MA
- LOPEZBARRIO, C;
Proceedings Of The International Test Conference (p. 409-418) - 1/12/1993
10.1109/test.1993.470671 Ver en origen
- iMarina
- iMarina
Este/a investigador/a no tiene documentos de trabajo.
Este/a investigador/a no tiene informes técnicos.
CARRYING OUT OF THALES ALENIA SPACE ESPAÑA YEAR ROUND CONTRACT FOR 2016-2017
- ALOU CERVERA, PEDRO (Colaborador/a)
- RIESGO ALCAIDE, TERESA (Colaborador/a)
- TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))
Ejecución: 01-09-2016 - 10-03-2022
Tipo: Interno
- iMarina
INVESTIGACIÓN DEL IMPACTO DE IMPLEMENTACIONES SEGURAS POST-CUÁNTICAS EN APLICACIONES IOT
- Rodriguez Medina, Alfonso (Colaborador/a)
- TORRE ARNANZ, EDUARDO DE LA (Colaborador/a)
- OTERO MARNOTES, JOSE ANDRES (Colaborador/a)
- PORTILLA BERRUECO, JORGE (Investigador principal (IP))
Ejecución: 09-03-2023 - 23-12-2023
Tipo: Interno
- iMarina
SecBluRed
- ALVAREZ-CAMPANA FDEZ.-CORREDOR, MANUEL (Investigador principal (IP))
- MARIN LOPEZ, ANDRES ISAAC (Participante)
- Villagrá González, Victor Abraham (Participante)
- Berrocal Colmenarejo, Julio José (Participante)
- OTERO MARNOTES, JOSE ANDRES (Participante)
- PORTILLA BERRUECO, JORGE (Investigador principal (IP))
- Rodriguez Medina, Alfonso (Participante)
- MUJICA ROJAS, GABRIEL NOE (Participante)
- TORRE ARNANZ, EDUARDO DE LA (Participante)
Ejecución: 22-12-2022 - 31-12-2025
Tipo: Nacional
- iMarina
INVESTIGACIÓN EXPERIMENTAL EN TECNOLOGÍAS INNOVADORAS PARA UNA COMUNIDAD ENERGÉTICA EFICIENTE Y SOSTENIBLE
- ALONSO ROMERO, ELISA (Participante)
- PEREZ MORENO, ERNESTO (Participante)
- ABANADES VELASCO, ALBERTO (Investigador principal (IP))
- MARTINEZ-VAL PEÑALOSA, JOSE MARIA (Participante)
- MUÑOZ ANTON, JAVIER (Participante)
- GONZALEZ PORTILLO, LUIS FRANCISCO (Participante)
- LOPEZ PANIAGUA, IGNACIO (Participante)
Ejecución: 15-12-2021 - 15-04-2024
Tipo: Nacional
Importe financiado: 550000,00 Euros.
- iMarina
TECNOCAI. Tecnologías eficientes e inteligentes orientadas a la salud y al confort en ambientes interiores.
- Rodriguez Medina, Alfonso (Participante)
- ZAMACOLA ALCALDE, RAFAEL MARIA (Participante)
- ZATO RECELLADO, José Gabriel (Investigador principal (IP))
- RIESGO ALCAIDE, TERESA (Investigador principal (IP))
- CECILIA FERNÁNDEZ-CONDE, LOURDES (Participante)
- PORTILLA BERRUECO, JORGE (Participante)
- MORENO GONZALEZ, FELIX ANTONIO (Participante)
- TORRE ARNANZ, EDUARDO DE LA (Participante)
- NARANJO HERNANDEZ, JOSE EUGENIO (Participante)
Ejecución: 01-12-2009 - 01-12-2012
Tipo: Nacional
Importe financiado: 26100,00 Euros.
- iMarina
Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems
- PORTILLA BERRUECO, JORGE (Director)
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Valverde Alcalá, Juan
1/1/2015
- iMarina
Design Methodologies and Architectures for Just-in-Time Hardware Composition of Multi Grain Reconfigurable Accelerators
- Otero Marnotes, Andrés (Director)
- TORRE ARNANZ, EDUARDO DE LA (Director)
- OTERO MARNOTES, JOSE ANDRES (Codirector) Doctorando: Zamacola Alcalde, Rafael María
4/7/2022
- iMarina
Runtime Adaptive Hardware/Software Execution in Complex Heterogeneous Systems
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Suriano, Leonardo
31/1/2021
- iMarina
A Framework to Support Run-Time Adaptation in Reconfigurable Multi-Accelerator Systems
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Rodríguez Medina, Alfonso
10/10/2020
- iMarina
Architecture and methodology for automated development of evolvable and reconfigurable hardware applications
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Mora de Sambricio, Javier
1/1/2019
- iMarina
Parametric and structural self-adaptation of embedded systems using evolvable hardware
- SEKANINA, Lukáš (Director)
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Salvador Perea, Rubén
1/1/2015
- iMarina
Run-Time Scalable Hardware for Reconfigurable Systems
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Otero Marnotes, Andres
1/1/2014
- iMarina
Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: He, Wei
1/1/2014
- iMarina
Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.
- TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Esteves Krasteva, Yana
1/1/2009
- iMarina
Este/a investigador/a no tiene patentes o licencias de software.
Grupos de investigación
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Grupo en Tecnología Electrónica Aplicada (GTEA)
Rol: Investigador Principal
Perfiles de investigador/a
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ORCID
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Publons
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Scopus Author ID