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Author profile at the institutional portal

Torre Arnanz, Eduardo De La eduardo.delatorre@upm.es

AUTOMÁTICA, INGENIERÍA ELÉCTRICA Y ELECTRÓNICA E INFORMÁTICA INDUSTRIAL / Universidad Politécnica de Madrid

Publications

Design, Synthesis, and Evaluation of Genistein Analogues as Anti-Cancer Agents

  • Xiong, Pahoua
  • Wang, Rubing
  • Zhang, Xiaojie
  • Dela Torre, Eduardo
  • Leon, Francisco
  • Zhang, Qiang
  • Zheng, Shilong
  • Wang, Guangdi
  • Chen, Qiao-Hong;
... View more Collapse

Anti-Cancer Agents In Medicinal Chemistry (p. 1197-1203) - 1/1/2015

10.2174/1871520615666150520142437 View at source

  • ISSN 18715206

Introduction to the Special Section on FPGAs Technology and Applications

  • Cumplido, Rene
  • Athanas, Peter
  • de la Torre, Eduardo;

Computers & Electrical Engineering (p. 67-68) - 1/1/2016

10.1016/j.compeleceng.2015.12.021 View at source

  • ISSN 00457906

Introduction to the special issue on FPGA Technology and Applications

  • Athanas, Peter
  • Cumplido, Rene
  • de la Torre, Eduardo;

Computers & Electrical Engineering (p. 1143-1145) - 1/1/2014

10.1016/j.compeleceng.2014.04.009 View at source

  • ISSN 00457906

Welcome to the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP) in Madrid, Spain

  • De La Torre E
  • Pillement S

Conference On Design And Architectures For Signal And Image Processing, Dasip - 1/1/2015

10.1109/dasip.2014.7115597 View at source

  • ISSN 21649766

Lossy hyperspectral image compression on a reconfigurable and fault-tolerant fpga-based adaptive computing platform†

  • Barrios Y
  • Rodríguez A
  • Sánchez A
  • Pérez A
  • López S
  • Otero A
  • de la Torre E
  • Sarmiento R
... View more Collapse

Electronics (p. 1-23) - 1/10/2020

10.3390/electronics9101576 View at source

  • ISSN 08834989

A dynamically reconfigurable BBNN architecture for scalable neuroevolution in hardware

  • García A
  • Zamacola R
  • Otero A
  • de la Torre E

Electronics - 1/5/2020

10.3390/electronics9050803 View at source

  • ISSN 08834989

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

  • Mora, Javier
  • Salvador, Ruben
  • de la Torre, Eduardo;

Genetic Programming And Evolvable Machines (p. 155-186) - 1/6/2019

10.1007/s10710-018-9340-5 View at source

  • ISSN 13892576

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

  • Zamacola, Rafael
  • Otero, Andres
  • Garcia, Alberto
  • De La Torre, Eduardo;

Ieee Access (p. 202133-202152) - 1/1/2020

10.1109/access.2020.3036541 View at source

  • ISSN 21693536

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

  • Pérez A
  • Rodríguez A
  • Otero A
  • Arjona DG
  • Jiménez-Peralo Á
  • Verdugo MÁ
  • De La Torre E
... View more Collapse

Ieee Access (p. 59891-59905) - 1/1/2020

10.1109/access.2020.2983308 View at source

  • ISSN 21693536

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

  • Suriano, Leonardo
  • Otero, Andres
  • Rodriguez, Alfonso
  • Sanchez-Renedo, Manuel
  • De la Torre, Eduardo;

Ieee Access (p. 118707-118724) - 1/1/2020

10.1109/access.2020.3005202 View at source

  • ISSN 21693536

FPGAs: Fundamentals, advanced features, and applications in industrial electronics

  • Andina JJR
  • de la Torre Arnanz E
  • Peña MDV

(p. 1-250) - 1/1/2017

10.1201/9781315162133 View at source

Wireless Sensor Networks: From Real World to System Integration - Alternative Hardware Approaches

  • Portilla J
  • Otero A
  • Rosello V
  • Valverde J
  • Krasteva Y
  • de la Torre E
  • Riesgo T
... View more Collapse

Comprehensive Materials Processing (p. 353-373) - 1/1/2014

10.1016/b978-0-08-096532-1.01313-3 View at source

Dynamic reconfigurable NoC (DRNoC) architecture: Application to fast NoC emulation

  • Krasteva Y
  • de la Torre E
  • Riesgo T

Dynamic Reconfigurable Network-On-Chip Design: Innovations For Computational Processing And Communication (p. 220-254) - 1/12/2010

10.4018/978-1-61520-807-4.ch009 View at source

Run-time scalable architecture for deblocking filtering in H.264/AVC and SVC video codecs

  • Teresa Cervero
  • S. López
  • G. Gallicó
  • OTERO MARNOTES, JOSE ANDRES
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA

Embedded Systems Design With Fpgas (p. 173-199) - 1/11/2013

10.1007/978-1-4614-1362-2_8 View at source

FPGAs and reconfigurable systems

  • Rodriguez-Andina JJ
  • de la Torre E

Fundamentals Of Industrial Electronics (p. 24-1-24-18) - 19/4/2016

  • iMarina

Adaptivity and Self-awareness of CPSs and CPSoSs

  • De La Torre E

Heterogeneous Cyber Physical Systems Of Systems (p. 37-60) - 1/1/2021

  • iMarina

Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs

  • Suriano L
  • Lima D
  • de la Torre E

16th International Symposium, Arc 2020 (p. 136-150) - 1/1/2020

10.1007/978-3-030-44534-8_11 View at source

Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems

  • Ortiz A
  • Zamacola R
  • Rodríguez A
  • Otero A
  • de la Torre E

16th International Symposium, Arc 2020 (p. 45-60) - 1/1/2020

10.1007/978-3-030-44534-8_4 View at source

INCREASING RELIABILITY OF COMMERCIAL RECONFIGURABLE MPSOC FPGAS FOR SPACE APPLICATIONS

  • Eduardo de la Torre Arranz

Hipeac 2020, European Network On High-Performance Embedded Architecture And Compilation (Bologna) - 20/1/2020

  • iMarina

Execution modeling in self-Aware FPGA-based architectures for efficient resource management

  • Cesar Castañares
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA
  • Rodriguez Medina, Alfonso
  • PORTILLA BERRUECO, JORGE

10th International Symposium On Reconfigurable And Communication-Centric Systems-On-Chip, Recosoc 2015 (p. 1-8) - 2/9/2015

10.1109/recosoc.2015.7238086 View at source

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

  • Mora J
  • Otero A
  • De La Torre E
  • Riesgo T

10th International Symposium On Reconfigurable And Communication-Centric Systems-On-Chip, Recosoc 2015 (p. 1-7) - 2/9/2015

10.1109/recosoc.2015.7238087 View at source

Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC

  • SURIANO, LEONARDO
  • TORRE ARNANZ, EDUARDO DE LA
  • Rodriguez Medina, Alfonso

12th International Symposium On Reconfigurable Communication-Centric Systems-On-Chip, Recosoc 2017 - Proceedings (p. 25-30) - 23/8/2017

10.1109/recosoc.2017.8016151 View at source

A Modular Peripheral to Support Self-Reconfiguration in SoCs

  • OTERO MARNOTES, JOSE ANDRES
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA
  • PORTILLA BERRUECO, JORGE

13th Euromicro Conference On Digital System Design: Architectures, Methods And Tools (p. 88-95) - 13/12/2010

10.1109/dsd.2010.100 View at source

Towards fine and medium grain dynamic functional extraction for HW/SW acceleration

  • Matev, V.
  • de la Torre, E.
  • Riesgo, T.;

2007 3rd Southern Conference On Programmable Logic, Proceedings (p. 93-+) - 27/9/2007

10.1109/spl.2007.371730 View at source

Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management

  • Krasteva Y
  • De La Torre E
  • Riesgo T

2007 Ieee International Symposium On Circuits And Systems, Vols 1-11 (p. 873-876) - 1/5/2007

10.1109/iscas.2007.378045 View at source

  • ISSN 02714310

Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes

  • S. Peter
  • P. Langendoerfer
  • O. Stecklina
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA
  • PORTILLA BERRUECO, JORGE

2009 6th Annual Ieee Communication Society Conference On Sensor, Mesh And Ad Hoc Communications And Networks Workshops (p. 224-+) - 16/11/2009

10.1109/sahcnw.2009.5172959 View at source

This researcher has no working papers.

This researcher has no technical reports.

CARRYING OUT OF THALES ALENIA SPACE ESPAÑA YEAR ROUND CONTRACT FOR 2016-2017

  • ALOU CERVERA, PEDRO (Colaborador/a)
  • RIESGO ALCAIDE, TERESA (Colaborador/a)
  • TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))

Period: 01-09-2016 - 10-03-2022

Type of funding: Internal

  • iMarina

INVESTIGACIÓN DEL IMPACTO DE IMPLEMENTACIONES SEGURAS POST-CUÁNTICAS EN APLICACIONES IOT

  • Rodriguez Medina, Alfonso (Colaborador/a)
  • TORRE ARNANZ, EDUARDO DE LA (Colaborador/a)
  • OTERO MARNOTES, JOSE ANDRES (Colaborador/a)
  • PORTILLA BERRUECO, JORGE (Investigador principal (IP))

Period: 09-03-2023 - 23-12-2023

Type of funding: Internal

  • iMarina

SecBluRed

  • ALVAREZ-CAMPANA FDEZ.-CORREDOR, MANUEL (Investigador principal (IP))
  • MARIN LOPEZ, ANDRES ISAAC (Participante)
  • Villagrá González, Victor Abraham (Participante)
  • Berrocal Colmenarejo, Julio José (Participante)
  • OTERO MARNOTES, JOSE ANDRES (Participante)
  • PORTILLA BERRUECO, JORGE (Investigador principal (IP))
  • Rodriguez Medina, Alfonso (Participante)
  • MUJICA ROJAS, GABRIEL NOE (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
... View more Collapse

Period: 22-12-2022 - 31-12-2025

Type of funding: National

  • iMarina

INVESTIGACIÓN EXPERIMENTAL EN TECNOLOGÍAS INNOVADORAS PARA UNA COMUNIDAD ENERGÉTICA EFICIENTE Y SOSTENIBLE

  • ALONSO ROMERO, ELISA (Participante)
  • PEREZ MORENO, ERNESTO (Participante)
  • ABANADES VELASCO, ALBERTO (Investigador principal (IP))
  • MARTINEZ-VAL PEÑALOSA, JOSE MARIA (Participante)
  • MUÑOZ ANTON, JAVIER (Participante)
  • GONZALEZ PORTILLO, LUIS FRANCISCO (Participante)
  • LOPEZ PANIAGUA, IGNACIO (Participante)
... View more Collapse

Period: 15-12-2021 - 15-04-2024

Type of funding: National

Amount of funding: 550000,00 Euros.

  • iMarina

TECNOCAI. Tecnologías eficientes e inteligentes orientadas a la salud y al confort en ambientes interiores.

  • Rodriguez Medina, Alfonso (Participante)
  • ZAMACOLA ALCALDE, RAFAEL MARIA (Participante)
  • ZATO RECELLADO, José Gabriel (Investigador principal (IP))
  • RIESGO ALCAIDE, TERESA (Investigador principal (IP))
  • CECILIA FERNÁNDEZ-CONDE, LOURDES (Participante)
  • PORTILLA BERRUECO, JORGE (Participante)
  • MORENO GONZALEZ, FELIX ANTONIO (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • NARANJO HERNANDEZ, JOSE EUGENIO (Participante)
... View more Collapse

Period: 01-12-2009 - 01-12-2012

Type of funding: National

Amount of funding: 26100,00 Euros.

  • iMarina

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

  • PORTILLA BERRUECO, JORGE (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Valverde Alcalá, Juan

1/1/2015

  • iMarina

Design Methodologies and Architectures for Just-in-Time Hardware Composition of Multi Grain Reconfigurable Accelerators

  • Otero Marnotes, Andrés (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director)
  • OTERO MARNOTES, JOSE ANDRES (Codirector) Doctorando: Zamacola Alcalde, Rafael María

4/7/2022

  • iMarina

Runtime Adaptive Hardware/Software Execution in Complex Heterogeneous Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Suriano, Leonardo

31/1/2021

  • iMarina

A Framework to Support Run-Time Adaptation in Reconfigurable Multi-Accelerator Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Rodríguez Medina, Alfonso

10/10/2020

  • iMarina

Architecture and methodology for automated development of evolvable and reconfigurable hardware applications

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Mora de Sambricio, Javier

1/1/2019

  • iMarina

Parametric and structural self-adaptation of embedded systems using evolvable hardware

  • SEKANINA, Lukáš (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Salvador Perea, Rubén

1/1/2015

  • iMarina

Run-Time Scalable Hardware for Reconfigurable Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Otero Marnotes, Andres

1/1/2014

  • iMarina

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: He, Wei

1/1/2014

  • iMarina

Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Esteves Krasteva, Yana

1/1/2009

  • iMarina

Emulación en prototipos basados en fpgas: métodos de depuración mediante inserción de lógica compatible con el estándar ieee-1149.1

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: GARCIA VALDERAS, Mario

1/1/2004

  • iMarina

This researcher has no patents or software licenses.

Last data update: 4/24/24 1:14 PM