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Perfil en el portal institucional

Torre Arnanz, Eduardo De La eduardo.delatorre@upm.es

AUTOMÁTICA, INGENIERÍA ELÉCTRICA Y ELECTRÓNICA E INFORMÁTICA INDUSTRIAL / Universidad Politécnica de Madrid

Actividades

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

  • Nunez-Yanez, J
  • Otero, A
  • de la Torre, E

Microprocessors And Microsystems - 1/4/2023

10.1016/j.micpro.2023.104801 Ver en origen

  • ISSN 01419331

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

  • Rodriguez A
  • Otero A
  • Platzner M
  • De la Torre E

Ieee Transactions On Computers (p. 2903-2914) - 1/1/2022

10.1109/tc.2021.3107196 Ver en origen

  • ISSN 00189340

A Machine-Learning-Based Distributed System for Fault Diagnosis with Scalable Detection Quality in Industrial IoT

  • Marino, R.
  • Wisultschew, C.
  • Otero, A.
  • Lanza-Gutierrez, J.M.
  • Portilla, J.
  • Torre, E.D.L.

Ieee Internet Of Things Journal (p. 4339-4352) - 1/1/2021

Editor: Institute of Electrical and Electronics Engineers Inc.

10.1109/jiot.2020.3026211 Ver en origen

  • ISSN 23274662
  • ISSN/ISBN 2327-4662

Multi-grain reconfigurable and scalable overlays for hardware accelerator composition

  • Zamacola R
  • Otero A
  • de la Torre E

Journal Of Systems Architecture - 1/1/2021

10.1016/j.sysarc.2021.102302 Ver en origen

  • ISSN 13837621

A dynamically reconfigurable BBNN architecture for scalable neuroevolution in hardware

  • García A
  • Zamacola R
  • Otero A
  • de la Torre E

Electronics - 1/5/2020

10.3390/electronics9050803 Ver en origen

  • ISSN 08834989

Lossy hyperspectral image compression on a reconfigurable and fault-tolerant fpga-based adaptive computing platform†

  • Barrios Y
  • Rodríguez A
  • Sánchez A
  • Pérez A
  • López S
  • Otero A
  • de la Torre E
  • Sarmiento R
... Ver más Contraer

Electronics (p. 1-23) - 1/10/2020

10.3390/electronics9101576 Ver en origen

  • ISSN 08834989

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

  • Pérez A
  • Rodríguez A
  • Otero A
  • Arjona DG
  • Jiménez-Peralo Á
  • Verdugo MÁ
  • De La Torre E
... Ver más Contraer

Ieee Access (p. 59891-59905) - 1/1/2020

10.1109/access.2020.2983308 Ver en origen

  • ISSN 21693536

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

  • Suriano, Leonardo
  • Otero, Andres
  • Rodriguez, Alfonso
  • Sanchez-Renedo, Manuel
  • De la Torre, Eduardo;

Ieee Access (p. 118707-118724) - 1/1/2020

10.1109/access.2020.3005202 Ver en origen

  • ISSN 21693536

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

  • Zamacola, Rafael
  • Otero, Andres
  • Garcia, Alberto
  • De La Torre, Eduardo;

Ieee Access (p. 202133-202152) - 1/1/2020

10.1109/access.2020.3036541 Ver en origen

  • ISSN 21693536

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

  • Mora, Javier
  • Salvador, Ruben
  • de la Torre, Eduardo;

Genetic Programming And Evolvable Machines (p. 155-186) - 1/6/2019

10.1007/s10710-018-9340-5 Ver en origen

  • ISSN 13892576

FPGAs: Fundamentals, advanced features, and applications in industrial electronics

  • Andina JJR
  • de la Torre Arnanz E
  • Peña MDV

(p. 1-250) - 1/1/2017

10.1201/9781315162133 Ver en origen

Adaptivity and Self-awareness of CPSs and CPSoSs

  • De La Torre E

Heterogeneous Cyber Physical Systems Of Systems (p. 37-60) - 1/1/2021

  • iMarina

FPGAs and reconfigurable systems

  • Rodriguez-Andina JJ
  • de la Torre E

Fundamentals Of Industrial Electronics (p. 24-1-24-18) - 19/4/2016

  • iMarina

Wireless Sensor Networks: From Real World to System Integration - Alternative Hardware Approaches

  • Portilla J
  • Otero A
  • Rosello V
  • Valverde J
  • Krasteva Y
  • de la Torre E
  • Riesgo T
... Ver más Contraer

Comprehensive Materials Processing (p. 353-373) - 1/1/2014

10.1016/b978-0-08-096532-1.01313-3 Ver en origen

Run-time scalable architecture for deblocking filtering in H.264/AVC and SVC video codecs

  • Teresa Cervero
  • S. López
  • G. Gallicó
  • OTERO MARNOTES, JOSE ANDRES
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA

Embedded Systems Design With Fpgas (p. 173-199) - 1/11/2013

10.1007/978-1-4614-1362-2_8 Ver en origen

Dynamic reconfigurable NoC (DRNoC) architecture: Application to fast NoC emulation

  • Krasteva Y
  • de la Torre E
  • Riesgo T

Dynamic Reconfigurable Network-On-Chip Design: Innovations For Computational Processing And Communication (p. 220-254) - 1/12/2010

10.4018/978-1-61520-807-4.ch009 Ver en origen

Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning

  • Otero A
  • Sanllorente G
  • de la Torre E
  • Nunez-Yanez J

Lecture Notes In Computer Science (p. 260-274) - 1/1/2023

10.1007/978-3-031-42921-7_18 Ver en origen

  • ISSN 03029743

Just-In-Time Composition of Reconfigurable Overlays

  • Zamacola R
  • Otero A
  • Rodríguez A
  • de la Torre E

Openaccess Series In Informatics - 1/1/2022

10.4230/oasics.parma-ditam.2022.2 Ver en origen

  • ISSN 21906807

A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution

  • Laserna J
  • Otero A
  • Torre Edl

Lecture Notes In Computer Science (p. 47-61) - 1/1/2022

10.1007/978-3-031-19983-7_4 Ver en origen

  • ISSN 03029743

Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays

  • Vázquez, D
  • Rodríguez, A
  • Otero, A
  • de la Torre, E

Dcis 2022 - Proceedings Of The 37th Conference On Design Of Circuits And Integrated Systems (p. 01-06) - 1/1/2022

10.1109/dcis55711.2022.9970069 Ver en origen

Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems

  • Encinas J
  • Rodriguez A
  • Otero A
  • De La Torre E

36th Conference On Design Of Circuits And Integrated Systems, Dcis 2021 (p. 94-100) - 1/1/2021

10.1109/dcis53048.2021.9666187 Ver en origen

INCREASING RELIABILITY OF COMMERCIAL RECONFIGURABLE MPSOC FPGAS FOR SPACE APPLICATIONS

  • Eduardo de la Torre Arranz

Hipeac 2020, European Network On High-Performance Embedded Architecture And Compilation (Bologna) - 20/1/2020

  • iMarina

Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs

  • Suriano L
  • Lima D
  • de la Torre E

16th International Symposium, Arc 2020 (p. 136-150) - 1/1/2020

10.1007/978-3-030-44534-8_11 Ver en origen

Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems

  • Ortiz A
  • Zamacola R
  • Rodríguez A
  • Otero A
  • de la Torre E

16th International Symposium, Arc 2020 (p. 45-60) - 1/1/2020

10.1007/978-3-030-44534-8_4 Ver en origen

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach

  • Palumbo F
  • Fanni T
  • Sau C
  • Rodríguez A
  • Madroñal D
  • Desnos K
  • Morvan A
  • Pelcat M
  • Rubattu C
  • Lazcano R
  • Raffo L
  • de la Torre E
  • Juárez E
  • Sanz C
  • Sánchez de Rojas P
... Ver más Contraer

Hardware/Software Self-Adaptation In Cps: The Cerbero Project Approach (p. 416-428) - 7/7/2019

10.1007/978-3-030-27562-4_30 Ver en origen

  • ISSN 03029743

Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems

  • OTERO MARNOTES, JOSE ANDRES
  • ORTIZ CUADRADO, ALBERTO
  • TORRE ARNANZ, EDUARDO DE LA
  • Rodriguez Medina, Alfonso

Data Transfer Modeling And Optimization In Reconfigurable Multi-Accelerator Systems (p. 20-26) - 1/7/2019

  • iMarina

Este/a investigador/a no tiene documentos de trabajo.

Este/a investigador/a no tiene informes técnicos.

WSN Development, Planning and Commissioning & Maintenance ToolSet

  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • MORENO GONZALEZ, FELIX ANTONIO (Participante)
  • PORTILLA BERRUECO, JORGE (Participante)
  • RIESGO ALCAIDE, TERESA (Investigador principal (IP))

Ejecución: 01-01-2011 - 31-12-2014

Tipo: Nacional

Importe financiado: 242569,60 Euros.

  • iMarina

Reconfigurable ultra-autonomous novel robots: RUNNER

  • Rodriguez Medina, Alfonso (Participante)
  • PORTILLA BERRUECO, JORGE (Participante)
  • RIESGO ALCAIDE, TERESA (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))

Ejecución: 01-12-2010 - 31-12-2013

Tipo: Nacional

Importe financiado: 55500,00 Euros.

  • iMarina

Reconfigurable Ultra-Autonomous Novel Robots

  • TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))

Ejecución: 01-12-2010 - 31-12-2013

Tipo: Internacional

  • iMarina

TECNOCAI. Tecnologías eficientes e inteligentes orientadas a la salud y al confort en ambientes interiores.

  • Rodriguez Medina, Alfonso (Participante)
  • ZAMACOLA ALCALDE, RAFAEL MARIA (Participante)
  • ZATO RECELLADO, José Gabriel (Investigador principal (IP))
  • RIESGO ALCAIDE, TERESA (Investigador principal (IP))
  • CECILIA FERNÁNDEZ-CONDE, LOURDES (Participante)
  • PORTILLA BERRUECO, JORGE (Participante)
  • MORENO GONZALEZ, FELIX ANTONIO (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • NARANJO HERNANDEZ, JOSE EUGENIO (Participante)
... Ver más Contraer

Ejecución: 01-12-2009 - 01-12-2012

Tipo: Nacional

Importe financiado: 26100,00 Euros.

  • iMarina

Reconfigurabilidad Dinámica para Escalabilidad en Redes Orientadas a Aplicaciones Multimedia

  • PORTILLA BERRUECO, JORGE (Participante)
  • SALVADOR PEREA, RUBEN (Participante)
  • OTERO MARNOTES, JOSE ANDRES (Participante)
  • MORENO GONZALEZ, FELIX ANTONIO (Participante)
  • TORROJA FUNGAIRIÑO, YAGO (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • RIESGO ALCAIDE, TERESA (Investigador principal (IP))
... Ver más Contraer

Ejecución: 01-01-2009 - 31-12-2011

Tipo: Nacional

  • iMarina

Real-time and dependability assessment of hw-accelerated space applications for reconfigurable MPSoCs

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Pérez García, Arturo

12/5/2023

  • iMarina

Design Methodologies and Architectures for Just-in-Time Hardware Composition of Multi Grain Reconfigurable Accelerators

  • Otero Marnotes, Andrés (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director)
  • OTERO MARNOTES, JOSE ANDRES (Codirector) Doctorando: Zamacola Alcalde, Rafael María

4/7/2022

  • iMarina

Runtime Adaptive Hardware/Software Execution in Complex Heterogeneous Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Suriano, Leonardo

31/1/2021

  • iMarina

A Framework to Support Run-Time Adaptation in Reconfigurable Multi-Accelerator Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Rodríguez Medina, Alfonso

10/10/2020

  • iMarina

Architecture and methodology for automated development of evolvable and reconfigurable hardware applications

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Mora de Sambricio, Javier

1/1/2019

  • iMarina

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

  • PORTILLA BERRUECO, JORGE (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Valverde Alcalá, Juan

1/1/2015

  • iMarina

Parametric and structural self-adaptation of embedded systems using evolvable hardware

  • SEKANINA, Lukáš (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Salvador Perea, Rubén

1/1/2015

  • iMarina

Run-Time Scalable Hardware for Reconfigurable Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Otero Marnotes, Andres

1/1/2014

  • iMarina

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: He, Wei

1/1/2014

  • iMarina

Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Esteves Krasteva, Yana

1/1/2009

  • iMarina

Este/a investigador/a no tiene patentes o licencias de software.

Última actualización de los datos: 24/04/24 13:14