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Author profile at the institutional portal

Torre Arnanz, Eduardo De La eduardo.delatorre@upm.es

AUTOMÁTICA, INGENIERÍA ELÉCTRICA Y ELECTRÓNICA E INFORMÁTICA INDUSTRIAL / Universidad Politécnica de Madrid

Publications

Hardware and software debugging of FPGA based microprocessor systems through debug logic insertion

  • Valderas M
  • de la Torre E
  • Ariza F
  • Riesgo T

Lecture Notes In Computer Science (p. 1057-1061) - 1/1/2004

  • ISSN 03029743
  • iMarina

Introduction to Special issue on FPGA Devices and Applications

  • Athanas, Peter
  • Cumplido, Rene
  • Feregrino-Uribe, Claudia
  • de la Torre, Eduardo;

Microprocessors And Microsystems (p. 843-844) - 1/1/2014

10.1016/j.micpro.2014.11.001 View at source

  • ISSN 01419331

Introduction to Special issue on Reconfigurable computing and FPGAs

  • Cumplido, Rene
  • de la Torre, Eduardo
  • Feregrino-Uribe, Claudia
  • Wirthlin, Michael;

Microprocessors And Microsystems (p. 541-542) - 29/10/2015

10.1016/j.micpro.2015.08.006 View at source

  • ISSN 01419331

Introduction to the Special Section on FPGAs Technology and Applications

  • Cumplido, Rene
  • Athanas, Peter
  • de la Torre, Eduardo;

Computers & Electrical Engineering (p. 67-68) - 1/1/2016

10.1016/j.compeleceng.2015.12.021 View at source

  • ISSN 00457906

Introduction to the special issue on FPGA Technology and Applications

  • Athanas, Peter
  • Cumplido, Rene
  • de la Torre, Eduardo;

Computers & Electrical Engineering (p. 1143-1145) - 1/1/2014

10.1016/j.compeleceng.2014.04.009 View at source

  • ISSN 00457906

Letter from the guest editors of the special issue on DCIS 2014

  • de la Torre E
  • Portilla J
  • Riesgo T

Microprocessors And Microsystems (p. 919-919) - 1/11/2015

10.1016/j.micpro.2015.11.006 View at source

  • ISSN 01419331

Lossy hyperspectral image compression on a reconfigurable and fault-tolerant fpga-based adaptive computing platform†

  • Barrios Y
  • Rodríguez A
  • Sánchez A
  • Pérez A
  • López S
  • Otero A
  • de la Torre E
  • Sarmiento R
... View more Collapse

Electronics (p. 1-23) - 1/10/2020

10.3390/electronics9101576 View at source

  • ISSN 08834989

Multi-grain reconfigurable and scalable overlays for hardware accelerator composition

  • Zamacola R
  • Otero A
  • de la Torre E

Journal Of Systems Architecture - 1/1/2021

10.1016/j.sysarc.2021.102302 View at source

  • ISSN 13837621

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

  • Mora, Javier
  • Salvador, Ruben
  • de la Torre, Eduardo;

Genetic Programming And Evolvable Machines (p. 155-186) - 1/6/2019

10.1007/s10710-018-9340-5 View at source

  • ISSN 13892576

Reconfigurable Networks on Chip: DRNoC architecture

  • Krasteva, Yana E.
  • de la Torre, Eduardo
  • Riesgo, Teresa;

Journal Of Systems Architecture (p. 293-302) - 1/7/2010

10.1016/j.sysarc.2010.04.003 View at source

  • ISSN 13837621

FPGAs: Fundamentals, advanced features, and applications in industrial electronics

  • Andina JJR
  • de la Torre Arnanz E
  • Peña MDV

(p. 1-250) - 1/1/2017

10.1201/9781315162133 View at source

Adaptivity and Self-awareness of CPSs and CPSoSs

  • De La Torre E

Heterogeneous Cyber Physical Systems Of Systems (p. 37-60) - 1/1/2021

  • iMarina

Dynamic reconfigurable NoC (DRNoC) architecture: Application to fast NoC emulation

  • Krasteva Y
  • de la Torre E
  • Riesgo T

Dynamic Reconfigurable Network-On-Chip Design: Innovations For Computational Processing And Communication (p. 220-254) - 1/12/2010

10.4018/978-1-61520-807-4.ch009 View at source

FPGAs and reconfigurable systems

  • Rodriguez-Andina JJ
  • de la Torre E

Fundamentals Of Industrial Electronics (p. 24-1-24-18) - 19/4/2016

  • iMarina

Run-time scalable architecture for deblocking filtering in H.264/AVC and SVC video codecs

  • Teresa Cervero
  • S. López
  • G. Gallicó
  • OTERO MARNOTES, JOSE ANDRES
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA

Embedded Systems Design With Fpgas (p. 173-199) - 1/11/2013

10.1007/978-1-4614-1362-2_8 View at source

Wireless Sensor Networks: From Real World to System Integration - Alternative Hardware Approaches

  • Portilla J
  • Otero A
  • Rosello V
  • Valverde J
  • Krasteva Y
  • de la Torre E
  • Riesgo T
... View more Collapse

Comprehensive Materials Processing (p. 353-373) - 1/1/2014

10.1016/b978-0-08-096532-1.01313-3 View at source

2D Reconfigurable Systolic Core Architecture for Evolvable Systems

  • OTERO MARNOTES, JOSE ANDRES
  • SALVADOR PEREA, RUBEN
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA

Proceedings (p. 327-332) - 15/11/2011

  • iMarina

A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time

  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA
  • Rodriguez Medina, Alfonso
  • PORTILLA BERRUECO, JORGE
  • MORA DE SAMBRICIO, JAVIER

Design & Architectures For Signal & Image Processing (Dasip) (p. 1-4) - 8/10/2014

  • iMarina

A Fast Emulation-Based NoC Prototyping Framework

  • Krasteva Y
  • Criado F
  • La Torre E
  • Riesgo T

International Conference On Reconfigurable Computing And Fpgas (Reconfig'08) (p. 211-216) - 3/12/2008

10.1109/reconfig.2008.74 View at source

A Modular Peripheral to Support Self-Reconfiguration in SoCs

  • OTERO MARNOTES, JOSE ANDRES
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA
  • PORTILLA BERRUECO, JORGE

13th Euromicro Conference On Digital System Design: Architectures, Methods And Tools (p. 88-95) - 13/12/2010

10.1109/dsd.2010.100 View at source

A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution

  • Laserna J
  • Otero A
  • Torre Edl

Lecture Notes In Computer Science (p. 47-61) - 1/1/2022

10.1007/978-3-031-19983-7_4 View at source

  • ISSN 03029743

A NOVEL SCALABLE DEBLOCKING FILTER ARCHITECTURE FOR H.264/AVC AND SVC VIDEO CODECS

  • Teresa Cervero
  • S. López
  • Roberto Sarmiento
  • G. Gallicó
  • OTERO MARNOTES, JOSE ANDRES
  • RIESGO ALCAIDE, TERESA
  • TORRE ARNANZ, EDUARDO DE LA
... View more Collapse

2011 Ieee International Conference On Multimedia And Expo (Icme) (p. 1-6) - 7/11/2011

10.1109/icme.2011.6012075 View at source

A Novel FPGA-based Evolvable Hardware System based on Multiple Processing Arrays

  • Gallego A
  • Mora J
  • Otero A
  • Salvador R
  • De La Torre E
  • Riesgo T

Proceedings - Ieee 27th International Parallel And Distributed Processing Symposium Workshops And Phd Forum, Ipdpsw 2013 (p. 182-191) - 20/5/2013

10.1109/ipdpsw.2013.56 View at source

A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm

  • Tu C
  • He W
  • Gao N
  • De La Torre E
  • Liu Z
  • Liu L

Proceeding On Ispec 2014 (p. 0-0) - 5/5/2014

10.1007/978-3-319-06320-1_17 View at source

  • ISSN 03029743

A Scalable Evolvable Hardware Processing Array

  • Gallego A
  • Mora J
  • Otero A
  • De La Torre E
  • Riesgo T

Proceedings Of International Conference On Reconfigurable Computing And Fpga (Reconfig) (p. 0-8) - 9/12/2013

10.1109/reconfig.2013.6732266 View at source

A Self-Tuned Thermal Compensation System for Reducing Process Variation Influence in Side-channel Attack Resistant Dual-rail Logic

  • He, Wei
  • Stottinger, Marc
  • de la Torre, Eduardo
  • Diaz, Veronica;

2015 Conference On Design Of Circuits And Integrated Systems, Dcis 2015 (p. 1-8) - 20/1/2016

10.1109/dcis.2015.7388574 View at source

This researcher has no working papers.

This researcher has no technical reports.

ALMACENAMIENTO INTELIGENTE BASADO EN BATERÍAS DE SEGUNDA VIDA PARA INTEGRACIÓN DE RENOVABLES

  • RIQUELME DOMINGUEZ, JOSE MIGUEL (Participante)
  • Castillo Sierra NA, Rafael (Miembro del equipo de trabajo)
  • Castillo Sierra NA, Rafael (Investigador/a)
  • RODRIGUEZ ARRIBAS, JAIME (Participante)
  • OTERO MARNOTES, JOSE ANDRES (Participante)
  • CASTRO FERNANDEZ, ROSA MARIA DE (Participante)
  • MARIÑO ANDRES, RODRIGO (Participante)
  • FRANCES ROGER, AIRAN (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • RAMIREZ PRIETO, DIONISIO (Investigador principal (IP))
... View more Collapse

Period: 01-12-2022 - 30-11-2024

Type of funding: National

Amount of funding: 166750,00 Euros.

  • iMarina

Actividad 4.7 del proyecto Investigación experimental en tecnologías innovadoras para una comunidad energética eficiente y sostenible

  • TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))

Period: 01-09-2021 - 31-12-2023

Type of funding: National

  • iMarina

An Advanced Circular and Agile Manufacturing Ecosystem based on rapid reconfigurable manufacturing process and individualized consumer preferences

  • Rodriguez Medina, Alfonso (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • ZAMACOLA ALCALDE, RAFAEL MARIA (Participante)
  • HERNANDEZ LORITE, ROGELIO (Participante)
  • ENCINAS ANCHUSTEGUI, JUAN (Participante)
  • PORTILLA BERRUECO, JORGE (Investigador principal (IP))
  • UCEDA ANTOLIN, JAVIER (Participante)
  • MUJICA ROJAS, GABRIEL NOE (Participante)
  • OTERO MARNOTES, JOSE ANDRES (Participante)
... View more Collapse

Period: 01-01-2020 - 31-12-2023

Type of funding: International

Amount of funding: 522625,00 Euros.

  • iMarina

Artificial Intelligence using Quantum measured Information for realtime distributed systems at the edge

  • GALLEGO ROMAN, JUAN (Miembro del equipo de trabajo)
  • KATEBZADEH, MARYAM (Miembro del equipo de trabajo)
  • Rodriguez Medina, Alfonso (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))
  • PORTILLA BERRUECO, JORGE (Participante)
  • OTERO MARNOTES, JOSE ANDRES (Participante)

Period: 01-12-2022 - 30-11-2025

Type of funding: National

Amount of funding: 249134,38 Euros.

  • iMarina

CARRYING OUT OF THALES ALENIA SPACE ESPAÑA YEAR ROUND CONTRACT FOR 2016-2017

  • ALOU CERVERA, PEDRO (Colaborador/a)
  • RIESGO ALCAIDE, TERESA (Colaborador/a)
  • TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))

Period: 01-09-2016 - 10-03-2022

Type of funding: Internal

  • iMarina

Co-sponsored PhD on: "Safe Reconfiguration of Hardware Accelerators on Multi-FPGA Platforms for Space Applications"

  • TORRE ARNANZ, EDUARDO DE LA (Investigador principal (IP))

Period: 01-10-2018 - 30-09-2021

Type of funding: International

Amount of funding: 90000,00 Euros.

  • iMarina

Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments

  • SALVADOR PEREA, RUBEN (Participante)
  • ORTIZ CUADRADO, ALBERTO (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • OTERO MARNOTES, JOSE ANDRES (Participante)
  • TORROJA FUNGAIRIÑO, YAGO (Participante)
  • GARRIDO GONZALEZ, MATIAS JAVIER (Participante)
  • RIESGO ALCAIDE, TERESA (Participante)
  • LANZA GUTIERREZ, JOSE MANUEL (Participante)
  • ZAMACOLA ALCALDE, RAFAEL MARIA (Participante)
  • Rodriguez Medina, Alfonso (Participante)
  • SANCHO ARAGON, JAIME (Participante)
  • MADROÑAL QUINTIN, DANIEL (Participante)
  • SURIANO, LEONARDO (Participante)
  • LAZCANO LOPEZ, RAQUEL (Participante)
  • SANZ ALVARO, CESAR (Participante)
  • GROBA GONZALEZ, ANGEL MANUEL (Participante)
  • JUAREZ MARTINEZ, EDUARDO (Investigador principal (IP))
... View more Collapse

Period: 01-01-2017 - 29-02-2020

Type of funding: International

Amount of funding: 337668,00 Euros.

  • iMarina

DESARROLLO DE UN SISTEMA DE CLASIFICACIÓN Y SELECCIÓN, EN TIEMPO REAL, DE MATERIALES DENTRO DEL FLUJO DE TRATAMIENTO DE LOS RESIDUOS SÓLIDOS URBANOS

  • OTERO MARNOTES, JOSE ANDRES (Investigador principal (IP))
  • TORRE ARNANZ, EDUARDO DE LA (Participante)
  • PORTILLA BERRUECO, JORGE (Participante)

Period: 01-03-2019 - 31-07-2021

Type of funding: National

Amount of funding: 92000,00 Euros.

  • iMarina

DESARROLLO EN PYTHON DE LA INTERFAZ GRÁFICA DEL DEMOSTRADOR

  • Rodriguez Medina, Alfonso (Colaborador/a)
  • TORRE ARNANZ, EDUARDO DE LA (Colaborador/a)
  • OTERO MARNOTES, JOSE ANDRES (Investigador principal (IP))

Period: 15-12-2020 - 10-03-2022

Type of funding: Internal

  • iMarina

DESARROLLO HERRAMIENTA SOFTWARE DE RESPUESTA EN TIEMPO REAL PARA OPTIMIZAR UNA FLOTA DE RECOGIDA SOSTENIBLE (GORDON 2.0)

  • PORTILLA BERRUECO, JORGE (Investigador principal (IP))
  • MUJICA ROJAS, GABRIEL NOE (Participante)
  • OTERO MARNOTES, JOSE ANDRES (Participante)
  • TORRE ARNANZ, EDUARDO DE LA (Participante)

Period: 29-06-2018 - 28-06-2020

Type of funding: National

Amount of funding: 30000,00 Euros.

  • iMarina

A Framework to Support Run-Time Adaptation in Reconfigurable Multi-Accelerator Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Rodríguez Medina, Alfonso

10/10/2020

  • iMarina

Architecture and methodology for automated development of evolvable and reconfigurable hardware applications

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Mora de Sambricio, Javier

1/1/2019

  • iMarina

Design Methodologies and Architectures for Just-in-Time Hardware Composition of Multi Grain Reconfigurable Accelerators

  • Otero Marnotes, Andrés (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director)
  • OTERO MARNOTES, JOSE ANDRES (Codirector) Doctorando: Zamacola Alcalde, Rafael María

4/7/2022

  • iMarina

Emulación en prototipos basados en fpgas: métodos de depuración mediante inserción de lógica compatible con el estándar ieee-1149.1

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: GARCIA VALDERAS, Mario

1/1/2004

  • iMarina

Parametric and structural self-adaptation of embedded systems using evolvable hardware

  • SEKANINA, Lukáš (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Salvador Perea, Rubén

1/1/2015

  • iMarina

Real-time and dependability assessment of hw-accelerated space applications for reconfigurable MPSoCs

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Pérez García, Arturo

12/5/2023

  • iMarina

Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Esteves Krasteva, Yana

1/1/2009

  • iMarina

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

  • PORTILLA BERRUECO, JORGE (Director)
  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Valverde Alcalá, Juan

1/1/2015

  • iMarina

Run-Time Scalable Hardware for Reconfigurable Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Otero Marnotes, Andres

1/1/2014

  • iMarina

Runtime Adaptive Hardware/Software Execution in Complex Heterogeneous Systems

  • TORRE ARNANZ, EDUARDO DE LA (Director) Doctorando: Suriano, Leonardo

31/1/2021

  • iMarina

This researcher has no patents or software licenses.

Last data update: 4/24/24 1:14 PM