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Author profile at the institutional portal

Ruiz Noguera, Mario Daniel mario.ruiz@uam.es

Tecnología electrónica y de las comunicaciones / Universidad Autónoma de Madrid

Publications

Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning

  • Alonso T
  • Petrica L
  • Ruiz M
  • Petri-Koenig J
  • Umuroglu Y
  • Stamelos I
  • Koromilas E
  • Blott M
  • Vissers K
... View more Collapse

Acm Transactions On Reconfigurable Technology And Systems - 1/6/2022

10.1145/3470567 View at source

  • ISSN 19367406

Demonstration of latency-aware 5G network slicing on optical metro networks

  • Shariati B
  • Velasco L
  • Pedreno-Manresa JJ
  • Dochhan A
  • Casellas R
  • Muqaddas A
  • Gonzalez De Dios O
  • Luque Canto L
  • Lent B
  • Lopez De Vergara JE
  • Lopez-Buedo S
  • Moreno F
  • Pavon P
  • Ruiz M
  • Patri SK
  • Giorgetti A
  • Cugini F
  • Sgambelluri A
  • Nejabati R
  • Simeonidou D
  • Braun RP
  • Autenrieth A
  • Elbers JP
  • Fischer JK
  • Freund R
... View more Collapse

Journal of Optical Communications and Networking (p. A81-A90) - 1/1/2022

10.1364/jocn.438951 View at source

  • ISSN 19430620

Modeling and Assessing Connectivity Services Performance in a Sandbox Domain

  • Ruiz M., Tabatabaeimehr F., Gifre L., López-Buedo S., De Vergara J.L., Gonzalez Ó., Velasco L.

Journal Of Lightwave Technology (p. 3180-3189) - 15/6/2020

10.1109/jlt.2020.2975641 View at source

  • ISSN 07338724

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks

  • Ruiz M., Ramos J., Sutter G., López De Vergara J., López-Buedo S., Aracil J.

Ieee Communications Magazine (p. 80-87) - 1/3/2016

10.1109/mcom.2016.7432152 View at source

  • ISSN 01636804

This researcher has no books.

This researcher has no book chapters.

Limago: An FPGA-based open-source 100 GbE TCP/IP stack

  • Ruiz M., Sidler D., Sutter G., Alonso G., Lopez-Buedo S.

Proceedings - 29th International Conference On Field-Programmable Logic And Applications, Fpl 2019 (p. 286-292) - 1/9/2019

10.1109/fpl.2019.00053 View at source

Towards 100 GbE FPGA-Based Flow Monitoring

  • Alonso T., Ruiz M., Sutter G., Lopez-Buedo S., Lopez De Vergara J.E.

2014 9th Southern Conference on Programmable Logic, SPL 2014 (p. 9-16) - 14/5/2019

10.1109/spl.2019.8714532 View at source

FPGA-based TCP/IP checksum offloading engine for 100 Gbps networks

  • Sutter, Gustavo
  • Ruiz, Mario
  • Lopez-Buedo, Sergio
  • Alonso, Gustavo;

2018 International Conference On Reconfigurable Computing And Fpgas, Reconfig 2018 - 13/2/2019

10.1109/reconfig.2018.8641729 View at source

An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks

  • Ruiz M., Sutter G., López-Buedo S., Zazo J.F., De Vergara J.E.L.

2017 International Conference On Reconfigurable Computing And Fpgas (Reconfig) - 2/2/2018

10.1109/reconfig.2017.8279776 View at source

  • ISBN 9781538637975

A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links

  • Zazo J., Lopez-Buedo S., Ruiz M., Sutter G.

2017 International Conference On Reconfigurable Computing And Fpgas (Reconfig) (p. 1-6) - 2/2/2018

10.1109/reconfig.2017.8279770 View at source

Submicrosecond latency video compression in a low-end FPGA-based system-on-chip

  • Alonso T., Ruiz M., Lopez Garcia-Arias A., Sutter G., Lopez De Vergara J.E.

Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018 (p. 355-359) - 9/11/2018

10.1109/fpl.2018.00067 View at source

Harnessing Programmable SoCs to Develop Cost-effective Network Quality Monitoring Devices

  • Ruiz, M.
  • Ramos, J.
  • Sutter, G.
  • Lopez-Buedo, S.
  • Lopez de Vergara, J. E.
  • Sisterna, C.;

Fpl 09: 19th International Conference On Field Programmable Logic And Applications - 26/9/2016

10.1109/fpl.2016.7577320 View at source

Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes

  • Ruizy M., Suttery G., Lopez-Buedo S., Ramosy J., De Vergara J., Aracil J.

2015 International Conference On Reconfigurable Computing And Fpgas, Reconfig 2015 - 25/1/2016

10.1109/reconfig.2015.7393325 View at source

FPGA-based encrypted network traffic identification at 100 Gbit/s

  • Ruiz M., Sutter G., Lopez-Buedo S., De Vergara J.E.L.

2016 International Conference On Reconfigurable Computing And Fpgas, Reconfig 2016 - 1/1/2016

10.1109/reconfig.2016.7857172 View at source

This researcher has no working papers.

This researcher has no technical reports.

This researcher has no research projects.

This researcher has no supervised thesis.

This researcher has no patents or software licenses.

Last data update: 3/18/24 10:21 PM