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Aranda Barjola, Luis Alberto luis.aranda@urjc.es

Ciencias de la Computación, Arquitectura de Computadores, Lenguajes y Sistemas Informáticos y Estadística e Investigación Operativa / Universidad Rey Juan Carlos

Publications

Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction

  • Garcia-Herrero, Francisco
  • Sanchez-Macian, Alfonso
  • San-Isidro, Mateo
  • Alberto Aranda, Luis
  • Antonio Maestro, Juan;

Ieee Transactions On Device And Materials Reliability (p. 390-394) - 1/6/2020

10.1109/tdmr.2020.2980754 View at source

  • ISSN 15304388

Analysis of the Critical Bits of a RISC-V Processor Implemented in an SRAM-Based FPGA for Space Applications

  • Alberto Aranda, Luis
  • Wessman, Nils-Johan
  • Santos, Lucana
  • Sanchez-Macian, Alfonso
  • Andersson, Jan
  • Weigand, Roland
  • Antonio Maestro, Juan;
... View more Collapse

Electronics - 1/1/2020

10.3390/electronics9010175 View at source

  • ISSN 08834989

An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform

  • Aranda, Luis Alberto
  • Sanchez-Macian, Alfonso
  • Maestro, Juan Antonio;

Ieee Transactions On Very Large Scale Integration (Vlsi) Systems (p. 1336-1340) - 1/5/2020

10.1109/tvlsi.2020.2969094 View at source

  • ISSN 10638210

ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs

  • Alberto Aranda, Luis
  • Sanchez-Macian, Alfonso
  • Antonio Maestro, Juan;

Ieee Access (p. 128153-128161) - 1/1/2019

10.1109/access.2019.2939858 View at source

  • ISSN 21693536

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

  • Alberto Aranda, Luis
  • Ruano, Oscar
  • Garcia-Herrero, Francisco
  • Antonio Maestro, Juan;

Ieee Transactions On Circuits And Systems Ii-Express Briefs (p. 1577-1581) - 1/1/2022

10.1109/tcsii.2021.3105558 View at source

  • ISSN 15497747

A Methodology to Analyze the Fault Tolerance of Demosaicking Methods against Memory Single Event Functional Interrupts (SEFIs)

  • Alberto Aranda, Luis
  • Sanchez-Macian, Alfonso
  • Antonio Maestro, Juan;

Electronics - 1/10/2020

10.3390/electronics9101619 View at source

  • ISSN 08834989

A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection

  • Alberto Aranda, Luis
  • Reviriego, Pedro
  • Antonio Maestro, Juan;

Ieee Transactions On Circuits And Systems Ii-Express Briefs (p. 376-380) - 1/3/2018

10.1109/tcsii.2017.2717490 View at source

  • ISSN 15497747

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Last data update: 7/14/23 1:56 PM