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Author profile at the institutional portal

Lopez Vallejo, M. Luisa m.lopez.vallejo@upm.es

INGENIERÍA ELECTRÓNICA / Universidad Politécnica de Madrid

Publications

Power considerations in banked CAMs: A leakage reduction approach

  • Echeverría P
  • Ayala J
  • López-Vallejo M

Vlsi Design - 26/5/2008

10.1155/2008/674259 View at source

  • ISSN 1065514X

A 0.0016 mm(2) 0.64 nJ Leakage-Based CMOS Temperature Sensor

  • Ituero, P
  • López-Vallejo, M
  • López-Barrio, C

Sensors (p. 12648-12662) - 18/9/2013

10.3390/s130912648 View at source

  • ISSN 14248220

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

  • Osuna, CG
  • Ituero, P
  • López-Vallejo, M

Sensors (p. 129-143) - 1/1/2014

10.3390/s140100129 View at source

  • ISSN 14248220

Welcome message

  • Camacho, D.
  • Yildirim, T.
  • Nguyen, N.T.
  • Badica, C.
  • Salcedo, S.

Plos One (p. xvi) - 24/9/2015

Editor: Institute of Electrical and Electronics Engineers Inc.

10.1109/inista.2015.7276717 View at source

  • ISBN 978-146739096-5
  • ISSN/ISBN 9781467390965

Democratizing science with the aid of parametric design and additive manufacturing: Design and fabrication of a versatile and low-cost optical instrument for scattering measurement

  • Nadal-Serrano, JM
  • Nadal-Serrano, A
  • Lopez-Vallejo, M

Plos One - 1/11/2017

10.1371/journal.pone.0187219 View at source

Simple method to generate calibrated synthetic smoke-like atmospheres at microscopic scale

  • Nadal-Serrano, JM
  • de la Pedrosa, EGG
  • Lopez-Vallejo, M
  • González, ADF
  • Lopez-Barrio, C

Plos One - 1/8/2019

10.1371/journal.pone.0220700 View at source

Self-controlled multilevel writing architecture for fast training in neuromorphic RRAM applications

  • Garcia-Redondo, F
  • Lopez-Vallejo, M

Nanotechnology - 31/7/2018

10.1088/1361-6528/aad2fa View at source

  • ISSN 09574484

Design of a pipelined hardware architecture for real-time neural network computations

  • Ayala, JL
  • Lomeña, AG
  • López-Vallejo, M
  • Fernández, A

Midwest Symposium On Circuits And Systems (p. I419-I422) - 1/1/2002

10.1109/mwscas.2002.1187247 View at source

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs

  • Echeverría, P
  • López-Vallejo, M

Microprocessors And Microsystems (p. 535-546) - 1/8/2011

10.1016/j.micpro.2011.04.004 View at source

  • ISSN 01419331

An rfid-based self-biased 40 nm low power ldo regulator for iot applications

  • Bahramali A
  • Lopez-Vallejo M

Micromachines - 1/1/2021

10.3390/mi12040396 View at source

  • ISSN 2072666X

This researcher has no books.

Diseño de memorias RAM estáticas BiCMOS de doble puerto

  • María Luisa López Vallejo
  • Rafael Burriel Lluna
  • Octavio Nieto-Taladriz

Viii Congreso Diseño De Circuitos Integrados: Málaga, 9 Al 11 De Noviembre De 1993 (p. 20-24) - 1/1/1993

  • iMarina

State-of-the-art SoC communication architectures

  • Ayala J
  • López-Vallejo M
  • Bertozzi D
  • Benini L

Embedded Systems: Handbook (p. 20-1) - 1/1/2005

10.1201/9781420038163 View at source

SoC communication architectures: From interconnection buses to packet-switched NoCs

  • Ayala J
  • López-Vallejo M
  • Bertozzi D
  • Benini L

Embedded Systems Design And Verification: Embedded Systems Handbook, Second Edition (p. 14-1) - 1/1/2009

  • iMarina

XHDL: Extending VHDL to improve core parameterization and reuse

  • Marcos, MAS
  • Herrero, AF
  • López-Vallejo, M

Advances In Design And Specification Languages For Socs: Selected Contributions From Fdl'04 (p. 217-235) - 1/12/2005

10.1007/0-387-26151-6_16 View at source

Temperature Monitoring Issues in Nanometer CMOS Integrated Circuits

  • Ituero P
  • López-Vallejo M

Advanced Circuits For Emerging Technologies (p. 483-507) - 7/5/2012

10.1002/9781118181508.ch19 View at source

A banked precomputation-based CAM architecture for low-power storage-demanding applications

  • Echeverria, P
  • Ayala, JL
  • Lopez-Vallejo, M

Proceedings Of The Mediterranean Electrotechnical Conference - Melecon (p. 57-60) - 1/12/2006

10.1109/melcon.2006.1653035 View at source

Analysis of the thermal impact of source-code transformations in embedded-processors

  • Ayala, JL
  • Méndez, C
  • López-Vallejo, M

Proceedings Of The Ieee International Conference On Electronics, Circuits, And Systems (p. 866-869) - 1/12/2006

10.1109/icecs.2006.379926 View at source

Assessing self-learning electronics through the support of remote labs

  • López-Vallejo M
  • Ituero P
  • Herrero A
  • García F

Proceedings Of The Iadis International Conference E-Learning 2011, Part Of The Iadis Multi Conference On Computer Science And Information Systems 2011, Mccsis 2011 (p. 446-452) - 1/12/2011

  • iMarina

Multi-way clustering techniques for system level partitioning

  • Vallejo, Mll
  • Lopez, Jcl

Proceedings Of The Annual Ieee International Asic Conference And Exhibit (p. 242-247) - 1/1/2001

10.1109/asic.2001.954705 View at source

  • ISSN 10630988

A low power 6T-SRAM using negative bit-line for variability tolerance beyond 22nm node

  • Royer P
  • López-Vallejo M

Proceedings Of The Acm Great Lakes Symposium On Vlsi, Glsvlsi (p. 37-42) - 30/5/2013

10.1145/2483028.2483056 View at source

Compilation for delay impact minimization in VLIW embedded systems

  • Ayala, JL
  • Atienza, D
  • Raghavan, P
  • López-Vallejo, M
  • Catthoor, F

Proceedings Of The 2017 32nd Ieee/Acm International Conference On Automated Software Engineering (Ase'17) (p. 83-+) - 1/12/2006

10.1109/iwias.2006.25 View at source

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm

  • Royer, P
  • García-Redondo, F
  • López-Vallejo, M

Proceedings Of The 2015 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2015 (p. 112-117) - 5/8/2015

10.1109/nanoarch.2015.7180596 View at source

A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs

  • Herrera-Alzu, I
  • López-Vallejo, M
  • Soriano, CG

Proceedings Of The 2015 Ieee International Symposium On Defect And Fault Tolerance In Vlsi And Nanotechnology Systems, Dfts 2015 (p. 72-75) - 2/11/2015

10.1109/dft.2015.7315138 View at source

A critical-path monitor for DVFS systems without datapath replication

  • Aparicio H
  • Ituero P
  • Lopez-Vallejo M

Proceedings Of The 2014 29th Conference On Design Of Circuits And Integrated Systems, Dcis 2014 (p. 1-5) - 1/1/2014

10.1109/dcis.2014.7035593 View at source

Implementation tradeoffs of triangle traversal algorithms for graphics processing

  • Royer P
  • Ituero P
  • Lopez-Vallejo M
  • Barrio C

Proceedings Of The 2014 29th Conference On Design Of Circuits And Integrated Systems, Dcis 2014 (p. 1-6) - 1/1/2014

10.1109/dcis.2014.7035578 View at source

This researcher has no working papers.

This researcher has no technical reports.

Efficient and Robust Hardware for Brain-Inspired Computin

  • MERINO BALAGUER, IRENE (Miembro del equipo de trabajo)
  • ALVAREZ MENDEZ, ANDRES ARTURO (Miembro del equipo de trabajo)
  • ROLDAN MADROÑERO, JOSE (Miembro del equipo de trabajo)
  • MENA PACHECO, JAVIER DE (Miembro del equipo de trabajo)
  • GARRIDO GALVEZ, MARIO (Miembro del equipo de trabajo)
  • GRACIA HERRANZ, AMADEO DE (Miembro del equipo de trabajo)
  • LÓPEZ ASUNCIÓN, SAMUEL (Miembro del equipo de trabajo)
  • LOPEZ VALLEJO, M. LUISA (Investigador principal (IP))
  • ITUERO HERRERO, PABLO (Investigador principal (IP))
  • AGUSTIN SAENZ, JAVIER (Participante)
  • RODRIGUEZ DOMINGUEZ, ANDRES (Participante)
  • LOPEZ BARRIO, CARLOS ALBERTO (Participante)
... View more Collapse

Period: 01-01-2019 - 31-12-2022

Type of funding: National

Amount of funding: 161777,00 Euros.

  • iMarina

Variabilidad en tecnologías nanométricas: tolerancia, fiabilidad y aprovechamiento

  • LÓPEZ ASUNCIÓN, SAMUEL (Investigador/a)
  • BAHRAMALI, ASGHAR (Miembro del equipo de trabajo)
  • LOPEZ VALLEJO, M. LUISA (Investigador principal (IP))
  • LOPEZ BARRIO, CARLOS ALBERTO (Participante)
  • ITUERO HERRERO, PABLO (Participante)

Period: 01-01-2016 - 31-12-2019

Type of funding: National

Amount of funding: 87241,00 Euros.

  • iMarina

Tolerancia a variaciones PVT y radiación en tecnologías nanométricas

  • ITUERO HERRERO, PABLO (Participante)
  • AGUSTIN SAENZ, JAVIER (Participante)
  • LOPEZ BARRIO, CARLOS ALBERTO (Participante)
  • GARCIA REDONDO, FERNANDO (Participante)
  • LOPEZ VALLEJO, M. LUISA (Investigador principal (IP))

Period: 01-01-2013 - 30-06-2017

Type of funding: National

  • iMarina

moBile, Autonomous and affordable SYstem to increase safety in Large unpredIctable environmentS

  • Grajal de la Fuente, Jesús (Investigador principal (IP))
  • YESTE OJEDA, OMAR ARTEMI (Participante)
  • LOPEZ VALLEJO, M. LUISA (Participante)
  • ITUERO HERRERO, PABLO (Participante)
  • LOPEZ BARRIO, CARLOS ALBERTO (Participante)

Period: 01-05-2011 - 30-04-2013

Type of funding: International

Amount of funding: 174748,00 Euros.

  • iMarina

Diseño electrónico avanzado: Consumo, temperatura y altas prestaciones

  • ECHEVERRIA ARAMENDI, PEDRO (Participante)
  • GARCIA REDONDO, FERNANDO (Miembro del equipo de trabajo)
  • SANZ HERVAS, ALFREDO (Participante)
  • ITUERO HERRERO, PABLO (Participante)
  • LOPEZ BARRIO, CARLOS ALBERTO (Participante)
  • LOPEZ VALLEJO, M. LUISA (Investigador principal (IP))

Period: 01-01-2010 - 31-12-2012

Type of funding: National

Amount of funding: 75503,80 Euros.

  • iMarina

THE APPLICATION OF NEUROMORPHIC PROCESSORS TO SATCOM APPLICATIONS

  • Velasco Martinez, Guillermo (Participante)
  • LOPEZ VALLEJO, M. LUISA (Investigador principal (IP))

Period: 05-05-2022 - 16-03-2023

  • iMarina

Autonomous sensing platform for structural monitoring of transmission towers.

  • Amadeo de Gracia Herranz (Investigador/a)
  • María Luisa López Vallejo (Investigador principal (IP))
  • MENA PACHECO, JAVIER DE (Investigador/a)

Period: 01-01-2022 - 31-12-2023

Type of funding: International

Amount of funding: 70000,00 Euros.

  • iMarina

Análisis tecnológico y desarrollo de técnicas de mitigación de fallos en la tecnología GF 22FDX” - CONVER2021.

  • María Luisa López Vallejo (Investigador principal (IP))
  • MENA PACHECO, JAVIER DE (Investigador/a)

Period: 01-09-2021 - 31-03-2022

  • iMarina

Prototipo de medida de velocidad y distancia

  • LOPEZ VALLEJO, M. LUISA (Investigador principal (IP))

Period: 01-09-2020 - 30-04-2021

Type of funding: National

Amount of funding: 12000,00 Euros.

  • iMarina

MISTI: Autonomous Synthetic Cells for Sensing Applications

  • MENA PACHECO, JAVIER DE (Investigador, Becario colaborador)
  • De Gracia Herranz A (Investigador/a)
  • De Mena Pacheco J (Investigador/a)
  • LOPEZ VALLEJO, M. LUISA (Investigador principal (IP))

Period: 01-01-2020 - 31-08-2021

Type of funding: International

Amount of funding: 25000,00 Euros.

  • iMarina

Variability-aware design of front-end circuits for self-powered applications

  • López Vallejo, María Luisa (Director) Doctorando: Bahramali, Asghar

13/4/2021

  • iMarina

Modeling and design of ring oscillators and their application in radiation environments

  • López Vallejo, María Luisa (Director)
  • LOPEZ VALLEJO, M. LUISA (Director) Doctorando: Agustín Sáenz, Javier

1/1/2017

  • iMarina

Study, design and validation of a framework model for smoke and particle-filled atmospheres

  • López Vallejo, María Luisa (Director)
  • LOPEZ VALLEJO, M. LUISA (Director) Doctorando: Nadal Serrano, José María

1/1/2017

  • iMarina

Resistive RAM: simulation and modeling for reliable design

  • López Vallejo, María Luisa (Director)
  • LOPEZ VALLEJO, M. LUISA (Director) Doctorando: García Redondo, Fernando

1/1/2017

  • iMarina

Design and simulation of deep nanometer SRAM cells under energy, mismatch, and radiation constraints

  • López Vallejo, Marisa (Director) Doctorando: Royer del Barrio, Pablo

1/1/2015

  • iMarina

Fault management techniques for systems with SRAM-based FPGAs

  • López Vallejo, Marisa (Director) Doctorando: Herrera Alzu, Ignacio

1/1/2015

  • iMarina

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

  • López Vallejo, María Luisa (Director) Doctorando: Sánchez Marcos, Miguel Ángel

1/1/2012

  • iMarina

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

  • López Vallejo, Marisa (Director) Doctorando: Ituero Herrero, Pablo

1/1/2012

  • iMarina

Hardware acceleration of Monte Carlo-based simulations

  • López Vallejo, María Luisa (Director) Doctorando: Echeverría Aramendi, Pedro

1/1/2011

  • iMarina

Power estimation and power optimization policies for processor-based systems

  • López Vallejo, María Luisa (Director) Doctorando: Ayala Rodrigo, José Luis

1/1/2005

  • iMarina

PROCEDIMIENTO Y ARQUITECTURA ELECTRONICA PARA LA DETECCION SOVA OPTIMA BASADO EN EL RASTREO DE PUNTOS DE FUSION

  • LOPEZ BARRIO, CARLOS ALBERTO (Inventores/autores/obtentores)
  • López Vallejo, María Luisa (Inventores/autores/obtentores)
  • ITUERO HERRERO, PABLO (Inventores/autores/obtentores)
  • ARRABAL AZZALINI,CARLOS (Inventores/autores/obtentores)

17/4/2008

  • iMarina

APARATO PARA LA MEDIDA DE TEMPERATURA Y CORRIENTE DE FUGAS EN UN CHIP.

  • López Vallejo, Marisa (Inventores/autores/obtentores)
  • AYALA RODRIGO, JOSE LUIS (Inventores/autores/obtentores)
  • ITUERO HERRERO,PABLO (Inventores/autores/obtentores)

7/7/2008

  • iMarina

VORRICHTUNG ZUR MESSUNG VON CHIP-LECKAGEFLUSS UND -TEMPERATUR

  • ITUERO HERRERO PABLO (Inventores/autores/obtentores)
  • AYALA RODRIGO JOSE LUIS (Inventores/autores/obtentores)
  • LOPEZ VALLEJO MARISA (Inventores/autores/obtentores)

27/7/2007

  • iMarina
Last data update: 4/24/24 1:19 PM